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6042as?atarm?23-dec-04 features incorporates the arm7tdmi ? arm ? thumb ? processor ? high-performance 32-bit risc architecture ? high-density 16-bit instruction set ? leader in mips/watt embedded ice in-circuit emulation, debug communication channel support 256 kbytes of internal high-speed flash, organized in 1024 pages of 256 bytes ? single cycle access at up to 30 mhz in worst case conditions ? prefetch buffer optimizing thumb instruction execution at maximum speed ? page programming time: 4 ms, including page auto-erase, full erase time: 10 ms ? 10,000 write cycles, 10-year data retention capability, sector lock capabilities 32k bytes of internal high-speed sram, single-cycle access at maximum speed memory controller (mc) ? embedded flash controller, abort status and misalignment detection ? memory protection unit reset controller (rstc) ? based on three power-on reset cells ? provides external reset signal shaping and reset sources status clock generator (ckgr) ? low-power rc oscillator, 3 to 20 mhz on-chip oscillator and one pll power management controller (pmc) ? power optimization capabilities, including slow clock mode (down to 500 hz), idle mode, standby mode and backup mode ? four programmable external clock signals advanced interrupt controller (aic) ? individually maskable, eight-level priority, vectored interrupt sources ? four external interrupt sources and one fast interrupt source, spurious interrupt protected debug unit (dbgu) ? 2-wire uart and support for debug communication channel interrupt, programmable ice access prevention periodic interval timer (pit) ? 20-bit programmable counter plus 12-bit interval counter windowed watchdog (wdt) ? 12-bit key-protected programmable counter ? provides reset or interrupt signal to the system ? counter may be stopped while the processor is in debug mode or in idle state real-time timer (rtt) ? 32-bit free-running counter with alarm ? runs off the internal rc oscillator two parallel input/output controllers (pio) ? sixty-two programmable i/o lines multiplexed with up to two peripheral i/os ? input change interrupt capability on each i/o line ? individually programmable open-drain, pull-up resistor and synchronous output shutdown controller (shdwc) ? programmable shutdown pin and wake-up circuitry four 32-bit battery backup registers for a total of 16 bytes one 8-channel 20-bit pwm controller (pmwc) one usb 2.0 full speed (12 mbits per second) device port ? on-chip transceiver, 2-kbyte configurable integrated fifos nineteen peripheral data controller (pdc) channels two can 2.0b active controllers, supporting 11-bit standard and 29-bit extended identifiers ? 16 fully programmable message object mailboxes, 16-bit time stamp counter two 8-channel 10-bit analog-to-digital converter at91 arm ? thumb ? -based microcontrollers AT91SAM7A3 summary preliminary note: this is a summary document. a complete document is available on our web site at www.atmel.com.
2 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 three universal synchronous/asynchronous receiver transmitters (usart) ? individual baud rate generator, irda infrared modulation/demodulation ? support for iso7816 t0/t1 smart card, hardware handshaking, rs485 support two master/slave serial peripheral interfaces (spi) ? 8- to 16-bit programmable data length, four external peripheral chip selects three 3-channel 16-bit timer/counters (tc) ? three external clock inputs, two multi-purpose i/o pins per channel ? double pwm generation, capture/waveform mode, up/down capability two synchronous serial controllers (ssc) ? independent clock and frame sync signals for each receiver and transmitter ? i2s analog interface support, time division multiplex support ? high-speed continuous data stream capabilities with 32-bit data transfer one two-wire interface (twi) ? master mode support only, all two-wire atmel eeprom?s supported multimedia card interface (mci) ? compliant with multimedia cards and sd cards ? automatic protocol control and fast automatic data transfers with pdc, mmc and sdcard compliant ieee 1149.1 jtag boundary scan on all digital pins required power supplies: ? embedded 1.8v regulator, drawing up to 100 ma for the core and the external components, enables 3.3v single supply mode ? 3.3 vddio i/o lines and flash power supply ? 1.8v vddcore core power supply ? 3v to 3.6v vddana analog power supply ? 3v to 3.6v vddbu backup power supply 5v-tolerant i/os fully static operation: 0 hz to 60 mhz at 1.65v and 85c worst case conditions available in a 100-lead lqfp package description the AT91SAM7A3 is a member of a series of 32-bit arm7 ? microcontrollers with an integrated can controller. it features a 256-kbyte high-speed flash and 32-kbyte sram, a large set of peripherals, including two 2.0b full can controllers, and a com- plete set of system functions minimizing the number of external components. the device is an ideal migration path for 8-bit microcontroller users looking for additional per- formance and extended memory. the embedded flash memory can be programmed in-system via the jtag-ice inter- face. built-in lock bits protect the firmware from accidental overwrite. the AT91SAM7A3 integrates a complete set of features facilitating debug, including a jtag in-circuit-emulation interface, misalignment detector, interrupt driven debug com- munication channel for user configurable trace on a console, and jtag boundary scan for board level debug and test. by combining a high-performance 32-bit risc processor with a high-density 16-bit instruction set, flash and sram memory, a wide range of peripherals including can controllers, 10-bit adc, timers and serial communication channels, on a monolithic chip, the AT91SAM7A3 is ideal for many compute-intensive embedded control applica- tions in the automotive, medical and industrial world.
3 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 block diagram figure 1. AT91SAM7A3 block diagram tf0 tk0 td0 rd0 rk0 rf0 tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 canrx0 cantx0 canrx1 cantx1 tf1 tk1 td1 rd1 rk1 rf1 tclk3 tclk4 tclk5 tioa3 tiob3 tioa4 tiob4 tioa5 tiob5 tclk6 tclk7 tclk8 tioa6 tiob6 tioa7 tiob7 tioa8 tiob8 twd twck pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 ddm ddp tdi tdo tms tck peripheral bridge peripheral data controller sram 32k bytes arm7tdmi processor ice jtag scan jtagsel usart0 ssc0 timer counter rxd0 txd0 sck0 rts0 cts0 npcs00 npcs01 npcs02 npcs03 miso0 mosi0 spck0 flash 256k bytes memory controller memory protection unit abort status address decoder misalignment detection pio pio apb embedded flash controller ad00 ad01 ad02 ad03 ad04 ad05 ad06 ad07 can0 adtrg0 19 channels pdc pdc usart1 rxd1 txd1 sck1 rts1 cts1 pdc pdc pdc pdc spi0 npcs10 npcs11 npcs12 npcs13 miso1 mosi1 spck1 pdc pdc spi1 pdc adc0 gndana vddana advrefp can1 pdc pdc ssc1 pdc pdc tc0 tc1 tc2 timer counter tc3 tc4 tc5 timer counter tc6 tc7 tc8 twi vddin gnd vddout rxd2 txd2 sck2 rts2 cts2 usart2 pdc pdc adc1 pdc adtrg1 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 pwmc 1.8 v voltage regulator mcck mccda mcda0-mcda3 mci pdc usb device fifo transceiver nrst fiq irq0-irq3 pck0-pck3 pmc aic pll rcosc piob reset controller drxd dtxd por pllrc osc xin xout por vddbu tst dbgu pdc pdc pio pit wdt rtt system controller vddio pioa por vddcore shutdown controller fwkup wkup0 wkup1 shdw gndbu vddbu gpbr pdc
4 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 signal description table 1 . signal description signal name function type active level comments power vddin 1.8v voltage regulator power supply power 2.7v to 3.6v vddio i/o lines and flash power supply power 3v to 3.6v vddbu backup i/o lines power supply power 3v to 3.6v vddana analog power supply power 3v to 3.6v vddout 1.8v voltage regulator output power 1.85v typical vddcore 1.8v core power supply power 1.65v to 1.95v vddpll 1.8v pll power supply power 1.65v to 1.95v gnd ground ground gndana analog ground ground gndbu backup ground ground gndpll pll ground ground clocks, oscillators and plls xin main oscillator input input xout main oscillator output output pllrc pll filter input pck0 - pck3 programmable clock output output shdw shut-down control output driven at 0v only. do not tie over vddbu wkup0 - wkup1 wake-up inputs input accept between 0v and vddbu fwkup force wake up input accept between 0v and vddbu ice and jtag tck test clock input no pull-up resistor tdi test data in input no pull-up resistor tdo test data out output tms test mode select input no pull-up resistor jtagsel jtag selection input pull-down resistor reset/test nrst microcontroller reset i/o low tst test mode select input pull-down resistor debug unit drxd debug receive data input dtxd debug transmit data output
5 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 aic irq0 - irq3 external interrupt inputs input fiq fast interrupt input input pio pa0 - pa31 parallel io controller a i/o pulled-up input at reset pb0 - pb29 parallel io controller b i/o pulled-up input at reset multimedia card interface mcck multimedia card clock output mccda multimedia card a command i/o mcda0 - mcda3 multimedia card a data i/o usb device port ddm usb device port data - analog ddp usb device port data + analog usart sck0 - sck1 - sck2 serial clock i/o txd0 - txd1 - txd2 transmit data i/o rxd0 - rxd1 - rxd2 receive data input rts0 - rts1 - rts2 request to send output cts0 - cts1 - cts2 clear to send input synchronous serial controller td0 - td1 transmit data output rd0 - rd1 receive data input tk0 - tk1 transmit clock i/o rk0 - rk1 receive clock i/o tf0 - tf1 transmit frame sync i/o rf0 - rf1 receive frame sync i/o timer/counter tclk0 - tclk8 external clock input input tioa0 - tioa8 i/o line a i/o tiob0 - tiob8 i/o line b i/o pwm controller pwm0 - pwm7 pwm channels output table 1 . signal description (continued) signal name function type active level comments
6 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 spi miso0-miso1 master in slave out i/o mosi0-mosi1 master out slave in i/o spck0-spck1 spi serial clock i/o npcs00-npcs10 spi peripheral chip select 0 i/o low npcs01 - npcs03 npcs11 - npcs13 spi peripheral chip select output low two-wire interface twd two-wire serial data i/o twck two-wire serial clock i/o analog-to-digital converter ad00-ad07 ad10-ad17 analog inputs analog digital pulled-up inputs at reset advrefp analog positive reference analog adtrg0 - adtrg1 adc trigger input can controller canrx0-canrx1 can inputs input cantx0-cantx1 can outputs output table 1 . signal description (continued) signal name function type active level comments
7 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 package and pinout 100-lead lqfp mechanical overview figure 2 shows the orientation of the 100-lead lqfp package. a detailed mechanical description is given in the section mechanical characteristics of the product datasheet. figure 2. 100-lead lqfp pinout (top view) pinout 51 76 75 50 26 25 1 100 table 2 . pinout in 100-lead lqfp package 1 gnd 26 vddbu 51 pa20 76 pllrc 2 nrst 27 fwkup 52 pa21 77 vddana 3 tst 28 wkup0 53 pa22 78 advrefp 4 pb13 29 wkup1 54 pa23 79 gndana 5 pb12 30 shdw 55 pa24 80 pb14/ad00 6 pb11 31 gndbu 56 pa25 81 pb15/ad01 7 pb10 32 pa4 57 pa26 82 pb16/ad02 8 pb9 33 pa5 58 pa27 83 pb17/ad03 9 pb8 34 pa6 59 vddcore 84 pb18/ad04 10 pb7 35 pa7 60 gnd 85 pb19/ad05 11 pb6 36 pa8 61 vddio 86 pb20/ad06 12 pb5 37 pa9 62 pa28 87 pb21/ad07 13 pb4 38 vddio 63 pa29 88 vddio 14 pb3 39 gnd 64 pa30 89 pb22/ad10 15 vddio 40 vddcore 65 pa31 90 pb23/ad11 16 gnd 41 pa10 66 jtagsel 91 pb24/ad12 17 vddcore 42 pa11 67 tdi 92 pb25/ad13 18 pb2 43 pa12 68 tms 93 pb26/ad14 19 pb1 44 pa13 69 tck 94 pb27/ad15 20 pb0 45 pa14 70 tdo 95 pb28/ad16 21 pa0 46 pa15 71 gnd 96 pb29/ad17 22 pa1 47 pa16 72 vddpll 97 ddm 23 pa2 48 pa17 73 xout 98 ddp 24 pa3 49 pa18 74 xin 99 vddout 25 gnd 50 pa19 75 gndpll 100 vddin
8 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 power considerations power supplies the AT91SAM7A3 has seven types of power supply pins: vddin pin. it powers the voltage regulator; voltage ranges from 2.7v to 3.6v, 3.3v nominal. if the voltage regulator is not used, vddin should be connected to gnd. vddio pin. it powers the i/o lines, the flash and the usb transceivers; voltage ranges from 3.0v to 3.6v, 3.3v nominal. vddout pin. it is the output of the 1.8v voltage regulator. vddcore pins. they power the logic of the device; voltage ranges from 1.65v to 1.95v, 1.8v typical. it might be connected to the vddout pin with decoupling capacitor. vddcore is required for the device, including its embedded flash, to operate correctly. vddpll pins. they power the pll; voltage ranges from 1.65v to 1.95v, 1.8v typical. they can be connected to the vddout pin with decoupling capacitor. vddbu pin. it powers the slow clock oscillator and the real time clock, as well as a part of the system controller; ranges from 3.0v and 3.6v, 3.3v nominal. vddana pin. it powers the adc; ranges from 3.0v and 3.6v, 3.3v nominal. separated ground pins are provided for vddpll, vddio, vddbu and vddana. the ground pins are respectively gndpll, gnd, gndbu and gndana. voltage regulator the AT91SAM7A3 embeds a voltage regulator that consumes less than 120 a static current and draws up to 100 ma of output current. adequate output supply decoupling is mandatory for vddout to reduce ripple and avoid oscillations. the best way to achieve this is to use two capacitors in parallel: one external 470 pf (or 1 nf) npo capacitor must be connected between vddout and gnd as close to the chip as possible. one external 3.3 f (or 4.7 f) x7r capacitor must be connected between vddout and gnd. adequate input supply decoupling is mandatory for vddin in order to improve startup stability and reduce source voltage drop. the input decoupling capacitor should be placed close to the chip. for example, two capacitors can be used in parallel: 100 nf npo and 4.7 f x7r.
9 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 typical powering schematics 3.3v single supply the AT91SAM7A3 supports a 3.3v single supply mode. the internal regulator is con- nected to the 3.3v source and its output feeds vddcore and vddpll. figure 3 shows the power schematics to be used for usb bus-powered systems. figure 3. 3.3v system single power supply schematics usb connector up to 5.5v 3.3v vddin voltage regulator vddout vddio vddana dc/dc converter vddcore vddpll vddbu
10 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 i/o lines considerations jtag port pins tms, tdi and tck are schmitt trigger inputs. tms and tck are 5v-tolerant, tdi is not. tms, tdi and tck do not integrate any resistors and have to be pulled-up externally. tdo is an output, driven at up to vddio. the jtagsel pin is used to select the jtag boundary scan when asserted at a high level. the jtagsel pin integrates a permanent pull-down resistor so that it can be left uncon- nected for normal operations. test pin the tst pin is used for manufacturing tests and integrates a pull-down resistor so that it can be left unconnected for normal operations. driving this line at a high level leads to unpredictable results. reset pin the nrst pin is bidirectional. it is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low exter- nally to reset the microcontroller. there is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. this allows connection of a simple push-button on the nrst pin as system user reset, and the use of the nrst signal to reset all the components of the system. pio controller a and b lines all the i/o lines pa0 to pa31 and pb0 to pb29 are 5v-tolerant and all integrate a pro- grammable pull-up resistor. programming of this pull-up resistor is performed independently for each i/o line through the pio controllers. 5v-tolerant means that the i/o lines can drive voltage level according to vddio, but can be driven with a voltage at up to 5.5v. however, driving an i/o line with a voltage over vddio while the programmable pull-up resistor is enabled can lead to unpredictable results. care should be taken, especially at reset, as all the i/o lines default as inputs with pull-up resistor enabled at reset. shutdown logic pins the shdw pin is an open drain output. it can be tied to vddbu with an external pull-up resistor. the fwup, wkup0 and wkup1 pins are input-only. they can accept voltages only between 0v and vddbu. it is recommended to tie these pins either to gnd or to vddbu with an external resistor. i/o line drive levels all the i/o lines can draw up to 2 ma.
11 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 processor and architecture arm7tdmi processor risc processor based on armv4t von neumann architecture ? runs at up to 60 mhz, providing 0.9 mips/mhz two instruction sets ? arm high-performance 32-bit instruction set ? thumb high code density 16-bit instruction set three-stage pipeline architecture ? instruction fetch (f) ? instruction decode (d) ?execute (e) debug and test features integrated embedded in-circuit emulator ? two watchpoint units ? test access port accessible through a jtag protocol ? debug communication channel debug unit ?two-pin uart ? debug communication channel interrupt handling ? chip id register ieee1149.1 jtag boundary-scan on all digital pins memory controller bus arbiter ? handles requests from the arm7tdmi and the peripheral data controller address decoder provides selection signals for ? three internal 1mbyte memory areas ? one 256 mbyte embedded peripheral area abort status registers ? source, type and all parameters of the access leading to an abort are saved ? facilitates debug by detection of bad pointers misalignment detector ? alignment checking of all data accesses ? abort generation in case of misalignment remap command ? remaps the internal sram in place of the embedded non-volatile memory ? allows handling of dynamic exception vectors 16-area memory protection unit ? individually programmable size between 1k bytes and 1m bytes ? individually programmable protection against write and/or user access ? peripheral protection against write and/or user access embedded flash controller ? embedded flash interface, up to three programmable wait states
12 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 ? read-optimized interface, buffering and anticipating the 16-bit requests, reducing the required wait states ? password-protected program, erase and lock/unlock sequencer ? automatic consecutive programming, erasing and locking operations ? interrupt generation in case of forbidden operation peripheral data controller handles data transfer between peripherals and memories nineteen channels ? two for each usart ? two for the debug unit ? two for each serial synchronous controller ? two for each serial peripheral interface ? one for the multimedia card interface ? one for each analog-to-digital converter low bus arbitration overhead ? one master clock cycle needed for a transfer from memory to peripheral ? two master clock cycles needed for a transfer from peripheral to memory next pointer management for reducing interrupt latency requirements
13 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 memory embedded memories 256 kbytes of flash memory ? 1024 pages of 256 bytes. ? fast access time, 30 mhz single cycle access in worst case conditions. ? page programming time: 4 ms, including page auto-erase ? full erase time: 10 ms ? 10,000 write cycles, 10-year data retention capability ? 16 lock bits, each protecting 64 pages 32 kbytes of fast sram ? single-cycle access at full speed memory mapping internal ram the AT91SAM7A3 embeds a high-speed 32-kbyte sram bank. after reset and until the remap command is performed, the sram is only accessible at address 0x0020 0000. after remap, the sram also becomes available at address 0x0. internal flash the AT91SAM7A3 features one bank of 256 kbytes of flash. the flash is mapped to address 0x0010 0000. it is also accessible at address 0x0 after the reset and before the remap command. figure 4. internal memory mapping 256m bytes flash before remap sram after remap undefined areas (abort) 0x000f ffff 0x001f ffff 0x002f ffff 0x0fff ffff 1m bytes 1m bytes 1m bytes 253m bytes internal flash internal sram 0x0000 0000 0x0010 0000 0x0020 0000 0x0030 0000
14 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 embedded flash flash organization the flash block of the AT91SAM7A3 is organized in 1024 pages of 256 bytes. it reads as 65,536 32-bit words. the flash block contains a 256-byte write buffer, accessible through a 32-bit interface. embedded flash controller the embedded flash controller (efc) manages accesses performed by the masters of the system. it enables reading the flash and writing the write buffer. it also contains a user interface mapped within the memory controller on the apb. the user interface allows: programming of the access parameters of the flash (number of wait states, timings, etc.) starting commands such as full erase, page erase, page program, nvm bit set, nvm bit clear, etc. getting the end status of the last command getting error status programming interrupts on the end of the last commands or on errors the embedded flash controller also provides a dual 32-bit prefetch buffer that opti- mizes 16-bit access to the flash. this is particularly efficient when the processor is running in thumb mode. lock regions the embedded flash controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. the AT91SAM7A3 has 16 lock regions. each lock region contains 64 pages of 256 bytes. each lock region has a size of 16 kbytes. the 16 nvm bits are software programmable through the efc user interface. the com- mand ?set lock bit? enables the protection. the command ?clear lock bit? unlocks the lock region.
15 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 system controller the system controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. figure 5. system controller block diagram nrst slck advanced interrupt controller periodic interval timer pa0-pa31 system controller watchdog timer pios controller power management controller pit_irq mck wdt_irq periph_irq{2..3] periph_nreset periph_clk[2..27] pck mck pmc_irq udpck nirq nfiq embedded peripherals periph_clk[2..3] pck[0-3] in out enable arm7tdmi slck fiq irq0-irq1-irq2-irq3 fiq periph_irq[4..26] periph_irq[2..27] int int periph_nreset periph_clk[4..26] ice_nreset proc_nreset periph_nreset dbgu_txd dbgu_rxd pit_irq rtt_irq dbgu_irq pmc_irq wdt_irq rstc_irq boundary scan tap controller jtag_nreset debug pck debug idle debug memory controller mck proc_nreset proc_nreset proc_nreset periph_nreset idle debug unit dbgu_irq mck dbgu_rxd periph_nreset force_ntrst dbgu_txd force_ntrst usb device port embedded flash udpck periph_nreset periph_clk[27] periph_irq[27] wkup1 shdw real-time timer reset controller periph_nreset wdt_fault wdrproc vddcore por proc_nreset rtt_irq slck flash_poe jtag_nreset rstc_irq slck periph_nreset shutdown controller vddbu por rcosc vddbu powered 4 general-purpose backup regs main osc xin xout mainck pll pllrc pllck pb0-pb29 vddcore powered wdt_fault wdrproc irq0-irq1-irq2-irq3 vddio por wkup0 fwkup ice_nreset
16 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 system controller mapping the system controller peripherals are all mapped to the highest 4k bytes of address space, between addresses 0xffff f000 and 0xffff ffff. each peripheral has an address space of 256 or 512 bytes, representing 64 or 128 registers. figure 6 shows the mapping of the system controller and of the memory controller figure 6. system controller mapping 0xffff f000 0xffff f200 0xffff f1ff 0xffff f3ff 0xffff f5ff 0xffff fbff 0xffff fcff 0xffff fd80 0xffff ffff 0xffff f400 0xffff f800 0xffff fc00 0xffff fd0f 0xffff fc2f 0xffff fc3f 0xffff fd4f 0xffff fc6f aic dbgu pioa reserved pmc mc advanced interrupt controller debug unit pio controller a power management controller memory controller 0xffff fd00 0xffff ff00 rstc pit rtt wdt reserved reserved gpbr 0xffff fd20 0xffff fd30 0xffff fd40 0xffff fd60 0xffff fd70 reset controller real-time timer periodic interval timer watchdog timer 512 bytes/128 registers 512 bytes/128 registers 512 bytes/128 registers 256 bytes/64 registers 16 bytes/4 registers 16 bytes/4 registers 16 bytes/4 registers 16 bytes/4 registers 256 bytes/64 registers general purpose backup registers 16 bytes/4 registers shdwc shutdown controller 16 bytes/4 registers 0xffff fc1f 0xffff fd10 reserved 0xffff f5ff 0xffff f600 piob pio controller b 512 bytes/128 registers peripheral name size address peripheral
17 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 reset controller the reset controller is based on three power-on reset cells. it gives the status of the last reset, indicating whether it is a general reset, a wake-up reset, a software reset, a user reset or a watchdog reset. in addition, it controls the internal resets and the nrst pin output. it shapes a signal on the nrst line, guaranteeing that the length of the pulse meets any requirement. clock generator the clock generator embeds one low-power rc oscillator, one main oscillator and one pll with the following characteristics: ? rc oscillator ranges between 22 khz and 42 khz ? main oscillator frequency ranges between 3 and 20 mhz ? main oscillator can be bypassed ? pll output ranges between 80 and 220 mhz it provides slck, mainck and pllck. figure 7. clock generator block diagram power management controller xin xout pllrc slow clock slck main clock mainck pll clock pllck control status embedded rc oscillator main oscillator pll and divider clock generator
18 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 power management controller the power management controller uses the clock generator outputs to provide: ? the processor clock pck ? the master clock mck ? the usb clock udpck ? all the peripheral clocks, independently controllable ? four programmable clock outputs the master clock (mck) is programmable from a few hundred hz to the maximum operating frequency of the device. the processor clock (pck) switches off when entering processor idle mode, thereby reducing power consumption while waiting an interrupt. figure 8. power management controller block diagram advanced interrupt controller controls the interrupt lines (nirq and nfiq) of the arm processor individually maskable and vectored interrupt sources ? source 0 is reserved for the fast interrupt input (fiq) ? source 1 is reserved for system peripherals (st, pmc, dbgu, etc.) ? other sources control the peripheral interrupts or external interrupts ? programmable edge-triggered or level-sensitive internal sources ? programmable positive/negative edge-triggered or high/low level-sensitive external sources 8-level priority controller ? drives the normal interrupt nirq of the processor ? handles priority of the interrupt sources ? higher priority interrupts can be served during service of a lower priority interrupt vectoring ? optimizes interrupt service routine branch and execution mck periph_clk[2..26] int udpck slck mainck pllck prescaler /1,/2,/4,...,/64 pck processor clock controller idle mode master clock controller peripherals clock controller on/off usb clock controller on/off slck mainck pllck prescaler /1,/2,/4,...,/64 programmable clock controller pllck divider /1,/2,/4 pck[0..3]
19 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 ? one 32-bit vector register per interrupt source ? interrupt vector register reads the corresponding current interrupt vector protect mode ? easy debugging by preventing automatic operations fast forcing ? permits redirecting any interrupt source on the fast interrupt general interrupt mask ? provides processor synchronization on events without triggering an interrupt debug unit comprises ? one two-pin uart ? one interface for the debug communication channel (dcc) support ? one set of chip id registers ? one interface allowing ice access prevention two-pin uart ? usart-compatible user interface ? programmable baud rate generator ? parity, framing and overrun error ? automatic echo, local loopback and remote loopback channel modes debug communication channel support ? offers visibility of commrx and commt x signals from the arm processor chip id registers ? identification of the device revision, sizes of the embedded memories, set of peripherals ? chip id is 0x170a0940 (version 0) period interval timer 20-bit programmable counter plus 12-bit interval counter watchdog timer 12-bit key-protected programmable counter running on prescaled slck provides reset or interrupt signals to the system counter may be stopped while the processor is in debug state or in idle mode real-time timer 32-bit free-running counter with alarm programmable 16-bit prescaler for sclk accuracy compensation shutdown controller software programmable assertion of the shdw open-drain pin de-assertion programmable with the pins wkup0, wkup1 and fwkup pio controllers a and b the pio controllers a and b respectively control 32 and 30 programmable i/o lines fully programmable through set/clear registers multiplexing of two peripheral functions per i/o line for each i/o line (whether assigned to a peripheral or used as general purpose i/o) ? input change interrupt ? half a clock period glitch filter
20 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 ? multi-drive option enables driving in open drain ? programmable pull up on each i/o line ? pin data status register, supplies visibility of the level on the pin at any time synchronous output, provides set and clear of several i/o lines in a single write
21 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 peripherals peripheral mapping each user peripheral is allocated 16k bytes of address space. figure 9. user peripherals mapping 16k bytes peripheral name peripheral address size 16k bytes 16k bytes 16k bytes 0xfffa 0000 0xfffa 3fff tc0, tc1, tc2 timer/counter 0, 1 and 2 16k bytes 16k bytes 16k bytes 16k bytes reserved reserved 0xfffa 4000 0xfffa 7fff tc3, tc4, tc5 timer/counter 3, 4 and 5 0xf000 0000 twi two-wire interface 0xfffb 8000 usart0 universal synchronous asynchronous receiver transmitter 0 0xfffc 0000 0xfffc 3fff usart1 universal synchronous asynchronous receiver transmitter 1 0xfffc 4000 0xfffc 7fff ssc0 serial synchronous controller 0 0xfffd 0000 0xfffd 3fff ssc1 serial synchronous controller 1 0xfffd 4000 0xfffd 7fff 0xfffd ffff spi0 serial peripheral interface 0 0xfffe 0000 0xfffe 3fff reserved 0xfffe ffff 0xfffe 8000 0xfffb 4000 0xfffb 7fff 16k bytes 0xfffa 8000 0xfffa bfff tc6, tc7, tc8 timer/counter 6, 7 and 8 16k bytes 0xfff8 0000 0xfff8 3fff can0 can controller 0 16k bytes 0xfff8 4000 0xfff8 7fff can1 can controller 1 reserved 0xfff8 8000 0xfff9 ffff 16k bytes 0xfffc ffff 16k bytes spi1 serial peripheral interface 1 0xfffe 4000 0xfffe 7fff 0xfff7 ffff 0xfffd 8000 0xfffd bfff adc0 analog-to-digital converter 0 16k bytes usart2 universal synchronous asynchronous receiver transmitter 1 0xfffc 8000 0xfffc bfff 0xfffc c000 0xfffb ffff reserved 0xfffb c000 0xfffb bfff 0xfffd c000 adc1 analog-to-digital converter 1 16k bytes pwmc 16k bytes 0xfffa c000 0xfffa ffff mci multimedia card interface 0xfffb 0000 0xfffb 3fff udp usb device port 16k bytes 16k bytes pwm controller
22 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 peripheral multiplexing on pio lines the AT91SAM7A3 features two pio controllers, pioa and piob, which multiplex the i/o lines of the peripheral set. pio controllers a and b control respectively 32 and 30 lines. each line can be assigned to one of two peripheral functions, a or b. some of them can also be multiplexed with analog input of both adc controllers. table 3 on page 23 and table 4 on page 24 define how the i/o lines of the peripherals a, b or analog input are multiplexed on the pio controllers a and b. the two columns ?function? and ?comments? have been inserted for the user?s own comments; they may be used to track how pins are defined in an application. note that some peripheral functions that are output only may be duplicated within both tables. at reset, all i/o lines are automatically configured as input with the programmable pull- up enabled, so that the device is maintained in a static state as soon as a reset occurs.
23 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 pio controller a multiplexing table 3 . multiplexing on pio controller a pio controller a application usage i/o line peripheral a peripheral b comment function comments pa 0 t w d a d t r g 0 pa1 twck adtrg1 pa 2 r x d 0 pa 3 t x d 0 pa 4 s c k 0 n p s c 1 0 pa5rts0npcs11 pa6 cts0 npcs12 pa7 rxd1 npcs13 pa 8 t x d 1 m i s o 1 pa 9 r x d 2 m o s i 1 pa10 txd2 spck1 pa11 npcs00 pa12 npcs01 mcda1 pa13 npcs02 mcda2 pa14 npcs03 mcda3 pa15 miso0 mcda0 pa16 mosi0 mccda pa17 spck0 mcck pa18 pwm0 pck0 pa19 pwm1 pck1 pa20 pwm2 pck2 pa21 pwm3 pck3 pa 2 2 p w m 4 i r q 0 pa 2 3 p w m 5 i r q 1 pa24 pwm6 tclk4 pa25 pwm7 tclk5 pa26 canrx0 pa27 cantx0 pa28 canrx1 tclk3 pa29 cantx1 tclk6 pa30 drxd tclk7 pa31 dtxd tclk8
24 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 pio controller b multiplexing table 4 . multiplexing on pio controller b pio controller b application usage i/o line peripheral a peripheral b comment function comments pb0 irq2 pwm5 pb1 irq3 pwm6 pb2 tf0 pwm7 pb3 tk0 pck0 pb4 td0 pck1 pb5 rd0 pck2 pb6 rk0 pck3 pb7 rf0 cantx1 pb8 fiq tf1 pb9 tclk0 tk1 pb10 tclk1 rk1 pb11 tclk2 rf1 pb12 tioa0 td1 pb13 tiob0 rd1 pb14 tioa1 pwm0 ad00 pb15 tiob1 pwm1 ad01 pb16 tioa2 pwm2 ad02 pb17 tiob2 pwm3 ad03 pb18 tioa3 pwm4 ad04 pb19 tiob3 npcs11 ad05 pb20 tioa4 npcs12 ad06 pb21 tiob4 npcs13 ad07 pb22 tioa5 ad10 pb23 tiob5 ad11 pb24 tioa6 rts1 ad12 pb25 tiob6 cts1 ad13 pb26 tioa7 sck1 ad14 pb27 tiob7 rts2 ad15 pb28 tioa8 cts2 ad16 pb29 tiob8 sck2 ad17
25 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 peripheral identifiers the AT91SAM7A3 embeds a wide range of peripherals. table 5 defines the peripheral identifiers of the AT91SAM7A3. unique peripheral identifiers are defined for both the aic and the pmc. note: 1. setting sysirq and adc bits in the clock set/clear registers of the pmc has no effect. the system controller and adc are continuously clocked. table 5. peripheral identifiers peripheral id peripheral mnemonic peripheral name external interrupt 0 aic advanced interrupt controller fiq 1sysirq (1) 2 pioa parallel i/o controller a 3 piob parallel i/o controller b 4 can0 can controller 0 5 can1 can controller 1 6 us0 usart 0 7 us1 usart 1 8 us2 usart 2 9 mci multimedia card interface 10 twi two-wire interface 11 spi0 serial peripheral interface 0 12 spi1 serial peripheral interface 1 13 ssc0 synchronous serial controller 0 14 ssc1 synchronous serial controller 1 15 tc0 timer/counter 0 16 tc1 timer/counter 1 17 tc2 timer/counter 2 18 tc3 timer/counter 3 19 tc4 timer/counter 4 20 tc5 timer/counter 5 21 tc6 timer/counter 6 22 tc7 timer/counter 7 23 tc8 timer/counter 8 24 adc0 (1) analog-to digital converter 0 25 adc1 (1) analog-to digital converter 1 26 pwmc pwm controller 27 udp usb device port 28 aic advanced interrupt controller irq0 29 aic advanced interrupt controller irq1 30 aic advanced interrupt controller irq2 31 aic advanced interrupt controller irq3
26 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 serial peripheral interface supports communication with external serial devices ? four chip selects with external decoder allow communication with up to 15 peripherals ? serial memories, such as dataflash ? and 3-wire eeproms ? serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors ? external co-processors master or slave serial peripheral bus interface ? 8- to 16-bit programmable data length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays per chip select between consecutive transfers and between clock and data ? programmable delay between consecutive transfers ? selectable mode fault detection ? maximum frequency at up to master clock two-wire interface master mode only compatibility with standard two-wire serial memories one, two or three bytes for slave address sequential read/write operations usart programmable baud rate generator 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb- or lsb-first ? optional break generation and detection ? by 8 or by 16 over-sampling receiver frequency ? hardware handshaking rts-cts ? receiver time-out and transmitter timeguard ? optional multi-drop mode with address generation and detection rs485 with driver control signal iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit irda modulation and demodulation ? communication at up to 115.2 kbps test modes ? remote loopback, local loopback, automatic echo serial synchronous controller provides serial synchronous communication links used in audio and telecom applications contains an independent receiver and transmitter and a common clock divider
27 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 offers a configurable frame sync and data length receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal receiver and transmitter include a data signal, a clock signal and a frame synchronization signal timer counter three 16-bit timer counter channels wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation ? delay timing ? pulse width modulation ? up/down capabilities each channel is user-configurable and contains: ? three external clock inputs ? five internal clock inputs as defined in table 6. ? two multi-purpose input/output signals ? two global registers that act on all three tc channels pwm controller eight channels, one 20-bit counter per channel common clock generator, providing thirteen different clocks ? a modulo n counter providing eleven clocks ? two independent linear dividers working on modulo n counter outputs independent channel programming ? independent enable/disable commands ? independent clock selection ? independent period and duty cycle, with double buffering ? programmable selection of the output waveform polarity ? programmable center or left aligned output waveform usb device port usb v2.0 full-speed compliant,12 mbits per second. embedded usb v2.0 full-speed transceiver six endpoints table 6. timer counter clock assignment tc clock input clock timer_clock1 mck/2 timer_clock2 mck/8 timer_clock3 mck/32 timer_clock4 mck/128 timer_clock5 mck/1024
28 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 ? endpoint 0: 8 bytes ? endpoint 1 and 2: 64 bytes ping-pong ? endpoint 3: 64 bytes ? endpoint 4 and 5: 512 bytes ping-pong embedded 2,376-byte dual-port ram for endpoints ? ping-pong mode (two memory banks) for isochronous and bulk endpoints suspend/resume logic multimedia card interface compatibility with multimedia card specification version 2.2 compatibility with sd memory card specification version 1.0 cards clock rate up to master clock divided by 2 embeds power management to slow down clock rate when not used supports up to sixteen slots (through multiplexing) ? one slot for one multimedia card bus (up to 30 cards) or one sd memory card supports stream, block and multi-block data read and write supports connection to peripheral data controller ? minimizes processor intervention for large buffer transfers can controller fully compliant with can 2.0b active controllers bit rates up to 1mbit/s 16 object-oriented mailboxes, each with the following properties: ? can specification 2.0 part a or 2.0 part b programmable for each message ? object-configurable as receive (with overwrite or not) or transmit ? local tag and mask filters up to 29-bit identifier/channel ? 32-bit access to data registers for each mailbox data object ? uses a 16-bit time stamp on receive and transmit messages ? hardware concatenation of id unmasked bit fields to speed up family id processing ? 16-bit internal timer for time stamping and network synchronization ? programmable reception buffer length up to 16 mailbox object ? priority management between transmission mailboxes ? autobaud and listening mode ? low power mode and programmable wake-up on bus activity or by the application ? data, remote, error and overload frame handling analog-to-digital converter 8-channel adc 10-bit 384k samples/sec successive approximation register adc -2/+2 lsb integral non linearity, -1/+2 lsb differential non linearity integrated 8-to-1 multiplexer, offering eight independent 3.3v analog inputs individual enable and disable of each channel external voltage reference for better accuracy on low-voltage inputs
29 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 multiple trigger sources ? hardware or software trigger ? external pins: adtrg0 and adtrg1 ? timer counter 0 to 5 outputs: tioa0 to tioa5 sleep mode and conversion sequencer ? automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels all analog inputs are shared with digital signals
30 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 ordering information table 7 . ordering information ordering code package temperature operating range AT91SAM7A3-aj 100-lead lqfp industrial (-40c to 85c)
31 preliminary AT91SAM7A3 preliminary 6042as?atarm?23-dec-04 document details title AT91SAM7A3 summary literature number 6042s revision history version a publication date: 23-dec-04
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